This invention relates to information processing systems and more particularly to a level machine type information processing system having a group of general purpose registers respectively corresponding to interruption process levels and being able to respond to an interruption to rapidly switch a processing on one level to a processing on another level.
In handling a plurality of interruption levels in an ordinary information processing system, when an interruption occurs during processing on a certain level, the interruption is permitted to be executed if it has higher priority than the presently processed level. For execution of the interruption, an address of an instruction next to an instruction presently executed and the contents of a general purpose register presently used have to be saved. Accordingly, some main memory areas or a plurality of save registers are needed and the save processing adds to processing time correspondingly.
Contrary to this, in an information processing system dedicated to level processing, a group of general purpose registers corresponding to interruption levels are provided, a level is processed using a general purpose register corresponding to that level and when an interruption causes processing to shift from one level to another, a general purpose register corresponding to the destined level is used, thereby eliminating the necessity of save and recovery processing of the contents of the general purpose register to and from the main memory.
An example of prior art level machine type information processing system is described as a central controller (CC) in an outline book of HITAC H-8633-2/3 type Communication Control Processing System, 8080-1-007, 1983.
Such a level machine type information processing system has instruction address registers (IAR's) corresponding to levels and a single lagging address register (LAR) provided in association with the IAR's. During processing of a level other than the level of the highest priority, an address of an instruction which precedes by one an instruction designated by an IAR is stored in the LAR and the contents of the LAR is updated concurrently with update of the contents of the IAR.
Upon occurrence of an interruption toward the level of the highest priority to a processing on a level other than the level of the highest priority, an address of an instruction executed immediately before the occurrence of the interruption or an address of an instruction preceding that executed instruction is stored in the LAR and update of the LAR is stopped when the interruption toward the level of the highest priority occurs. This ensures that after start of a processing on the level of the highest priority, the address of the instruction processed immediately before the interruption can be determined from the contents of the LAR.
The above prior art system has, however, the following disadvantages.
In the first place, since the prior art system is such that only when an interruption toward the level of the highest priority occurs, an address of an instruction executed immediately before the occurrence of the interruption can be held in the LAR, an address of an immediately previously executed instruction can not be obtained from the LAR when an interruption toward other level than the level of the highest priority occurs. Therefore, the prior art system can not realize a hierarchial structure for a routine wherein a predetermined processing is carried out by referring to the state of a preceding process level which is pausing, for example, an error recovery routine. When taking a program interruption, for instance, an interruption due to an error of program is an abnormal phenomenon but an interruption due to page absence is not an abnormal phenomenon. Accordingly, it is desirable that these interruptions be processed on different levels. Preferably, the interruption process due to an error of program may be allocated to, for example, the level of the highest priority (level 1) and the interruption process due to page absence may be allocated to for example, a level which is second in priority (level 2). In the prior art system, when an error of program occurs and an interruption toward the level 1 takes place during a processing on a certain level, an address of an instruction, on the interrupted level, which raises the error can be known by examining the contents of the LAR during a processing on the level 1. But when the page absence occurs and an interruption toward the level 2 takes place, an address of an instruction, on the interrupted level, which raises the page absence can not be known during a processing on the level 2. Accordingly, with the prior art system, in order for an interrupting process routine executed during page absence to know an address of an instruction which raises the page absence, priority of the level 1 has to be given to the interrupting process routine, thus preventing hierarchy of interruption processes and realization of software simplified for preparation and maintenance.
In the second place, the EXECUTE instruction generally used in the general purpose computer can not be added to the instruction set of the prior art system and the instruction set can not be used in common for both the system for general purpose and system dedicated to level processing. This problem will be explained with reference to FIGS. 16 and 17.
In the prior art system, an EXIT instruction issued on the level of the lowest priority (level 5) is so prescribed as to be a supervisor call (SVC) toward or destined for a level which is higher in priority than the level 5 by one, that is, level 4 and accordingly, when an EXIT instruction 140 is issued at an A address 142 in a routine on the level 5 as shown in FIG. 16, an interruption occurs and the processing shifts to the level 4. An interruption decision circuit examines the contents of an interruption factor register to know that the interruption factor is the SVC. In this case, a B address (head address of parameter 141) 143 is recorded in an IAR corresponding to the level 5 and therefore the parameter 141 can be used during a processing on the level 4. Further, since the length of the parameter 141 per se is also recorded in the parameter 141, a C address 144 (=B address+parameter length) standing for a return address to the processing on level 5 can be known.
Assume now that an EXECUTE instruction is added to an instruction set. The EXECUTE instruction is defined such that when this instruction is executed, an instruction at an address designated within the EXECUTE instruction, that is, a target instruction is partly changed using a general purpose register designated within the EXECUTE instruction and then, the target instruction is executed.
The interruption toward the level 4 by the SVC may occur in either of mode (a) due to an EXIT instruction alone (see FIG. 16) and mode (b) due to a target instruction of EXECUTE instruction standing for an EXIT instruction (see FIG. 17) but the two modes can not be discriminated from each other.
The instruction length of the EXIT instruction is of 2 bytes but the EXECUTE instruction required to designate an address of the target instruction and an address of the general purpose register has a length longer than that of the EXIT instruction. Because of the difference in length between EXIT and EXECUTE instructions 151 and 150, in the mode (b), an A address 153 in FIG. 17 can not be determined from the contents of an IAR for level 5 (recording a B address 154 in FIG. 17) during a processing on the level 4. Accordingly, a D address 155 can not be determined, either, resulting in a failure to use a parameter 152 and it is undetermined whether the B address stands for a return address to a processing on the level 5.
For the reasons described previously, the EXECUTE instruction can not be added to the instruction set in the prior art level machine. However, the EXECUTE instruction has many applications and is exemplarily used when data of different lengths can be moved, with the procedure part of program inhibited from being written, by defining a target instruction of the EXECUTE instruction as a move character (MVC) instruction and designating a length of data to be moved according to the MVC instruction by a value in a general purpose register designated by the EXECUTE instruction. The variable length processing is frequently used in various software processings including a processing of fields having different lengths dependent on packets in a packet header, which processing occurs in software for communications (for example, address fields of X.25 layer 3).
Accordingly, when the EXECUTE instruction is not permitted to be used, the procedure part of program has to be rewritten each time movement of data of different lengths is effected and must not be inhibited from being written, which may cause runaway of the program.
In another application, the EXECUTE instruction is used in a program for tracing a program, that is, a tracer.
The tracer has the following four portions (a) to (d):
(a) Operation resembling instruction execution operation effected using hardware in the ordinary information processing system and including recognition and and inspection of an instruction code of an instruction, scheduled to be executed in a program to be traced, and of register and memory area used is carried out, the instruction code is recorded in order to record which instruction is executed, and other necessary information is recorded;
(b) The above instruction is actually executed under the direction of the EXECUTE instruction;
(c) After execution of the instruction, the contents of the general purpose register, memory area, condition code, and so on are recorded; and
(d) The contents of the register designating the address of the instruction is updated in order that an instruction to be executed subsequently to the above instruction can be traced, and the procedure is returned to the portion (a).
By using such a tracer, record of various kinds of information unavailable from a tracer based on hardware can be obtained to simplify preparation and maintenance of programs. However, when the use of the EXECUTE instruction is not permitted, the aforementioned tracer can not be prepared.